1. Field of the Invention
Exemplary embodiments of the present disclosure relate to an apparatus for detecting a cut-off frequency of a pulse signal, and a method thereof, and more particularly to an apparatus for detecting a cut-off frequency of a pulse signal configured to detect a frequency of a pulse signal, in a case a frequency of an inputted pulse signal rises above a maximum rated speed, and a method thereof.
2. Description of Related Art
A problem occurs, in a case a frequency of a pulse signal rises above a maximum rated speed in a case a pulse signal generated from an encoder or a pulse generator is processed. To be more specific, a high speed counter module of a PLC (Programmable Logic Controller) functions to count a fast pulse signal of a pulse generator or an encoder that cannot be counted by a general counter instruction.
FIG. 1 is a block diagram illustrating a high speed counter module according to prior art. A high speed counter module (12) of FIG. 1 includes a buffer (12-1), an MPU (Micro Process Unit, 12-2) and an input circuit (12-3).
The input circuit (12-3) converts a high speed pulse train generated by an encoder (13) to a CMOS level and transmits it to the MPU (12-2), where the MPU (12-2) adds or deducts a buffer (12-1) value from a rising edge or a falling edge of an inputted pulse signal. A management unit (11) including a PC (Personal Computer) or an HMI (Human Machine Interface) reads the buffer (12-1) value of the high speed counter module (12) and displays it on a screen.
FIG. 2 is a schematic view illustrating a process in a case a pulse train (string) is inputted to an input contact point of the high speed counter module (12) according to prior art.
The MPU (12-2) repetitively processes a user program (scan program) (S22) after initializing an I/O (Input/Output) and a memory (S21). That is, the MPU (12-2) executes a PLC scan program (S23), communicates with the management unit (11) and updates an input/output contact point (S25).
Whenever the rising/falling edges of the input signal are detected during these processes, the PLC scan program is stopped to generate an interrupt signal, and a high speed counter process routine is performed.
However, the method of performing the high speed counter function after interrupting the PLC scan program and generating interrupt whenever the signal inputted to an interrupt port rises (1, 3) or falls (2, 4) suffers from many disadvantages.
That is, interrupts may be continuously accumulated to greatly slow or stop the scan program performance, if an edge occurrence period (Tin) of an input pulse train is shorter (if a maximum input speed is exceeded) than a maximum interrupt enabling time (T). Although the MPU (12-2) may measure the number of the pulse inputs accumulated during a predetermined unit time and check if a set maximum input allowable speed has been exceeded in order to prevent this phenomenon, this process suffers from disadvantages in that an additional routine for measuring the number of accumulated pulses whenever the interrupt is processed to increase each interrupt process time and to decrease the performance of high speed counter module.